1. Field of the Invention
The present invention relates generally to semiconductor packaging technology and automated wire bonding.
2. Description of the Related Art
In a semiconductor packaging process, wire-bonding techniques may be used to form electrical interconnections between an integrated circuit (IC) chip and a next-level substrate, for example a lead frame. As IC chips have become more integrated, smaller, and/or faster, the bond pads, provided on the IC chip, have tended to increase in number while tending to become smaller, for example in area and/or pitch. As a result, the number of bonding wires may also increase which may cause the pitch to decrease, thus making the wire bonding process more complicated.
In advanced type packages, for example, multi-pin packages, chip-stack packages, or multi-bonded packages, the wire bonding process may require that a large quantity of information be put into a wire bonder. In the past, an engineer may have been responsible for entering information manually into a wire bonder, thus an appreciable amount of time may have been required for configuring a wire bonding process.
A conventional approach for managing an automated wire bonding process may include an integrated management system. The integrated management system may automatically execute a procedure for reviewing and editing an assembly reference, and a bonding specification used for manufacturing IC chip packages. The integrated management system may also include a drawing management system (DMS) for creating an assembly reference, and a bonding specification drawing system which may create a bonding specification, based on the assembly reference.